library verilog;
use verilog.vl_types.all;
entity mux_RegDst is
    port(
        a1              : in     vl_logic_vector(4 downto 0);
        a0              : in     vl_logic_vector(4 downto 0);
        rw              : out    vl_logic_vector(4 downto 0);
        RegDst          : in     vl_logic
    );
end mux_RegDst;
